/*
 * ARM Limited (ARM) is supplying this software for use with Cortex-M
 * processor based microcontroller, but can be equally used for other
 * suitable processor architectures. This file can be freely distributed.
 * Modifications to this file shall be clearly marked.
 * 
 * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
 * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
 * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
 * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
 *
 * @file     output/MEC1743_QSZ.h
 * @brief    CMSIS HeaderFile
 * @version  1.2
 * @date     19. May 2024
 * @note     Generated by SVDConv V3.3.42 on Sunday, 19.05.2024 10:19:49
 *           from File 'output/MEC1743_QSZ.svd',
 * 
 * MEC174x information Copyright 2024 Microchip Technologies Inc.
 */


/** @addtogroup Microchip Technolgy Inc.
  * @{
  */


/** @addtogroup MEC1743_QSZ
  * @{
  */


#ifndef MEC1743_QSZ_H
#define MEC1743_QSZ_H

#ifdef __cplusplus
extern "C" {
#endif


/** @addtogroup Configuration_of_CMSIS
  * @{
  */



/* =========================================================================================================================== */
/* ================                                Interrupt Number Definition                                ================ */
/* =========================================================================================================================== */

typedef enum {
/* =======================================  ARM Cortex-M4 Specific Interrupt Numbers  ======================================== */
  Reset_IRQn                = -15,              /*!< -15  Reset Vector, invoked on Power up and warm reset                     */
  NonMaskableInt_IRQn       = -14,              /*!< -14  Non maskable Interrupt, cannot be stopped or preempted               */
  HardFault_IRQn            = -13,              /*!< -13  Hard Fault, all classes of Fault                                     */
  MemoryManagement_IRQn     = -12,              /*!< -12  Memory Management, MPU mismatch, including Access Violation
                                                     and No Match                                                              */
  BusFault_IRQn             = -11,              /*!< -11  Bus Fault, Pre-Fetch-, Memory Access Fault, other address/memory
                                                     related Fault                                                             */
  UsageFault_IRQn           = -10,              /*!< -10  Usage Fault, i.e. Undef Instruction, Illegal State Transition        */
  SVCall_IRQn               =  -5,              /*!< -5 System Service Call via SVC instruction                                */
  DebugMonitor_IRQn         =  -4,              /*!< -4 Debug Monitor                                                          */
  PendSV_IRQn               =  -2,              /*!< -2 Pendable request for system service                                    */
  SysTick_IRQn              =  -1,              /*!< -1 System Tick Timer                                                      */
/* ========================================  MEC1743_QSZ Specific Interrupt Numbers  ========================================= */
  MEC_GIRQ08_IRQn           =   0,              /*!< 0  ECIA Aggregated GIRQ 08                                                */
  MEC_GIRQ09_IRQn           =   1,              /*!< 1  ECIA Aggregated GIRQ 09                                                */
  MEC_GIRQ10_IRQn           =   2,              /*!< 2  ECIA Aggregated GIRQ 10                                                */
  MEC_GIRQ11_IRQn           =   3,              /*!< 3  ECIA Aggregated GIRQ 11                                                */
  MEC_GIRQ12_IRQn           =   4,              /*!< 4  ECIA Aggregated GIRQ 12                                                */
  MEC_GIRQ13_IRQn           =   5,              /*!< 5  ECIA Aggregated GIRQ 13                                                */
  MEC_GIRQ14_IRQn           =   6,              /*!< 6  ECIA Aggregated GIRQ 14                                                */
  MEC_GIRQ15_IRQn           =   7,              /*!< 7  ECIA Aggregated GIRQ 15                                                */
  MEC_GIRQ16_IRQn           =   8,              /*!< 8  ECIA Aggregated GIRQ 16                                                */
  MEC_GIRQ17_IRQn           =   9,              /*!< 9  ECIA Aggregated GIRQ 17                                                */
  MEC_GIRQ18_IRQn           =  10,              /*!< 10 ECIA Aggregated GIRQ 18                                                */
  MEC_GIRQ19_IRQn           =  11,              /*!< 11 ECIA Aggregated GIRQ 19                                                */
  MEC_GIRQ20_IRQn           =  12,              /*!< 12 ECIA Aggregated GIRQ 20                                                */
  MEC_GIRQ21_IRQn           =  13,              /*!< 13 ECIA Aggregated GIRQ 21                                                */
  MEC_GIRQ23_IRQn           =  14,              /*!< 14 ECIA Aggregated GIRQ 23                                                */
  MEC_GIRQ24_IRQn           =  15,              /*!< 15 ECIA Aggregated GIRQ 24                                                */
  MEC_GIRQ25_IRQn           =  16,              /*!< 16 ECIA Aggregated GIRQ 25                                                */
  MEC_GIRQ26_IRQn           =  17,              /*!< 17 ECIA Aggregated GIRQ 26                                                */
  MEC_I2C_SMB0_IRQn         =  20,              /*!< 20 I2C_SMB0 interrupt                                                     */
  MEC_I2C_SMB1_IRQn         =  21,              /*!< 21 I2C_SMB1 interrupt                                                     */
  MEC_I2C_SMB2_IRQn         =  22,              /*!< 22 I2C_SMB2 interrupt                                                     */
  MEC_I2C_SMB3_IRQn         =  23,              /*!< 23 I2C_SMB3 interrupt                                                     */
  MEC_DMA_CH00_IRQn         =  24,              /*!< 24 DMA Channel 0 interrupt                                                */
  MEC_DMA_CH01_IRQn         =  25,              /*!< 25 DMA Channel 1 interrupt                                                */
  MEC_DMA_CH02_IRQn         =  26,              /*!< 26 DMA Channel 2 interrupt                                                */
  MEC_DMA_CH03_IRQn         =  27,              /*!< 27 DMA Channel 3 interrupt                                                */
  MEC_DMA_CH04_IRQn         =  28,              /*!< 28 DMA Channel 4 interrupt                                                */
  MEC_DMA_CH05_IRQn         =  29,              /*!< 29 DMA Channel 5 interrupt                                                */
  MEC_DMA_CH06_IRQn         =  30,              /*!< 30 DMA Channel 6 interrupt                                                */
  MEC_DMA_CH07_IRQn         =  31,              /*!< 31 DMA Channel 7 interrupt                                                */
  MEC_DMA_CH08_IRQn         =  32,              /*!< 32 DMA Channel 8 interrupt                                                */
  MEC_DMA_CH09_IRQn         =  33,              /*!< 33 DMA Channel 9 interrupt                                                */
  MEC_DMA_CH10_IRQn         =  34,              /*!< 34 DMA Channel 10 interrupt                                               */
  MEC_DMA_CH11_IRQn         =  35,              /*!< 35 DMA Channel 11 interrupt                                               */
  MEC_DMA_CH12_IRQn         =  36,              /*!< 36 DMA Channel 12 interrupt                                               */
  MEC_DMA_CH13_IRQn         =  37,              /*!< 37 DMA Channel 13 interrupt                                               */
  MEC_DMA_CH14_IRQn         =  38,              /*!< 38 DMA Channel 14 interrupt                                               */
  MEC_DMA_CH15_IRQn         =  39,              /*!< 39 DMA Channel 15 interrupt                                               */
  MEC_UART0_IRQn            =  40,              /*!< 40 UART 0 interrupt                                                       */
  MEC_UART1_IRQn            =  41,              /*!< 41 UART 1 interrupt                                                       */
  MEC_EMI0_IRQn             =  42,              /*!< 42 EMI 0 interrupt                                                        */
  MEC_EMI1_IRQn             =  43,              /*!< 43 EMI 1 interrupt                                                        */
  MEC_EMI2_IRQn             =  44,              /*!< 44 EMI 2 interrupt                                                        */
  MEC_ACPI_EC0_IBF_IRQn     =  45,              /*!< 45 ACPI EC 0 IBF interrupt                                                */
  MEC_ACPI_EC0_OBE_IRQn     =  46,              /*!< 46 ACPI EC 0 OBE interrupt                                                */
  MEC_ACPI_EC1_IBF_IRQn     =  47,              /*!< 47 ACPI EC 1 IBF interrupt                                                */
  MEC_ACPI_EC1_OBE_IRQn     =  48,              /*!< 48 ACPI EC 1 OBE interrupt                                                */
  MEC_ACPI_EC2_IBF_IRQn     =  49,              /*!< 49 ACPI EC 2 IBF interrupt                                                */
  MEC_ACPI_EC2_OBE_IRQn     =  50,              /*!< 50 ACPI EC 2 OBE interrupt                                                */
  MEC_ACPI_EC3_IBF_IRQn     =  51,              /*!< 51 ACPI EC 3 IBF interrupt                                                */
  MEC_ACPI_EC3_OBE_IRQn     =  52,              /*!< 52 ACPI EC 3 OBE interrupt                                                */
  MEC_ACPI_EC4_IBF_IRQn     =  53,              /*!< 53 ACPI EC 4 IBF interrupt                                                */
  MEC_ACPI_EC4_OBE_IRQn     =  54,              /*!< 54 ACPI EC 4 OBE interrupt                                                */
  MEC_ACPI_PM1_CTL_IRQn     =  55,              /*!< 55 ACPI PM1 0 control interrupt                                           */
  MEC_ACPI_PM1_EN_IRQn      =  56,              /*!< 56 ACPI PM1 0 enable interrupt                                            */
  MEC_ACPI_PM1_STS_IRQn     =  57,              /*!< 57 ACPI PM1 0 status interrupt                                            */
  MEC_KBC0_OBE_IRQn         =  58,              /*!< 58 KBC 0 output buffer empty interrupt                                    */
  MEC_KBC0_IBF_IRQn         =  59,              /*!< 59 KBC 0 input buffer full interrupt                                      */
  MEC_MBOX0_IRQn            =  60,              /*!< 60 Mailbox 0 interrupt                                                    */
  MEC_BDP0_IRQn             =  62,              /*!< 62 BDP 0 interrupt                                                        */
  MEC_PECI0_IRQn            =  70,              /*!< 70 PECI0 interrupt                                                        */
  MEC_TACH0_IRQn            =  71,              /*!< 71 TACH 0 interrupt                                                       */
  MEC_TACH1_IRQn            =  72,              /*!< 72 TACH 1 interrupt                                                       */
  MEC_TACH2_IRQn            =  73,              /*!< 73 TACH 2 interrupt                                                       */
  MEC_RPMFAN0_FAIL_IRQn     =  74,              /*!< 74 RPMFAN 0 fail interrupt                                                */
  MEC_RPMFAN0_STALL_IRQn    =  75,              /*!< 75 RPMFAN 0 stall interrupt                                               */
  MEC_RPMFAN1_FAIL_IRQn     =  76,              /*!< 76 RPMFAN 1 fail interrupt                                                */
  MEC_RPMFAN1_STALL_IRQn    =  77,              /*!< 77 RPMFAN 1 stall interrupt                                               */
  MEC_ADC0_SGL_IRQn         =  78,              /*!< 78 ADC Single(one-shot) conversion done interrupt                         */
  MEC_ADC0_RPT_IRQn         =  79,              /*!< 79 ADC Repeat conversion done interrupt                                   */
  MEC_RCID0_IRQn            =  80,              /*!< 80 RC-ID 0 interrupt                                                      */
  MEC_RCID1_IRQn            =  81,              /*!< 81 RC-ID 1 interrupt                                                      */
  MEC_RCID2_IRQn            =  82,              /*!< 82 RC-ID 2 interrupt                                                      */
  MEC_BBLED0_IRQn           =  83,              /*!< 83 LED0 interrupt                                                         */
  MEC_BBLED1_IRQn           =  84,              /*!< 84 LED1 interrupt                                                         */
  MEC_BBLED2_IRQn           =  85,              /*!< 85 LED2 interrupt                                                         */
  MEC_BBLED3_IRQn           =  86,              /*!< 86 LED3 interrupt                                                         */
  MEC_PHOT_IRQn             =  87,              /*!< 87 PROCHOT interrupt                                                      */
  MEC_QSPI0_IRQn            =  91,              /*!< 91 QSPI0 controller interrupt                                             */
  MEC_GSPI0_IRQn            =  92,              /*!< 92 GSPI v2 instance 0 interrupt                                           */
  MEC_GSPI1_IRQn            =  94,              /*!< 94 GSPI v2 instance 1 interrupt                                           */
  MEC_BCL0_ERR_IRQn         =  96,              /*!< 96 BC-Link 0 error interrupt                                              */
  MEC_BCL0_BCLR_IRQn        =  97,              /*!< 97 BC-Link 0 busy clear interrupt                                         */
  MEC_PS2CTL0_ACT_IRQn      = 100,              /*!< 100  PS2 Controller 0 Active interrupt                                    */
  MEC_PS2CTL1_ACT_IRQn      = 101,              /*!< 101  PS2 Controller 1 Active interrupt                                    */
  MEC_ESPI_PC_IRQn          = 103,              /*!< 103  eSPI IO Peripheral Channel interrupt                                 */
  MEC_ESPI_BM1_IRQn         = 104,              /*!< 104  eSPI IO Bus Master 1 interrupt                                       */
  MEC_ESPI_BM2_IRQn         = 105,              /*!< 105  eSPI IO Bus Master 2 interrupt                                       */
  MEC_ESPI_LTR_IRQn         = 106,              /*!< 106  eSPI IO LTR interrupt                                                */
  MEC_ESPI_OOB_UP_IRQn      = 107,              /*!< 107  eSPI IO OOB channel upstream transfer interrupt                      */
  MEC_ESPI_OOB_DN_IRQn      = 108,              /*!< 108  eSPI IO OOB channel downstream transfer interrupt                    */
  MEC_ESPI_FC_IRQn          = 109,              /*!< 109  eSPI IO Flash channel interrupt                                      */
  MEC_ESPI_RST_IRQn         = 110,              /*!< 110  eSPI IO Edge detected on ESPI_RESET signal                           */
  MEC_RTMR0_IRQn            = 111,              /*!< 111  RTOS Timer 0 interrupt                                               */
  MEC_HTMR0_IRQn            = 112,              /*!< 112  Hibernation timer 0 interrupt                                        */
  MEC_HTMR1_IRQn            = 113,              /*!< 113  Hibernation timer 1 interrupt                                        */
  MEC_WKTMR0_ALARM_IRQn     = 114,              /*!< 114  Week timer 0 alarm interrupt                                         */
  MEC_WKTMR0_SUBWK_IRQn     = 115,              /*!< 115  Week timer 0 sub-week alarm interrupt                                */
  MEC_WKTMR0_ONESEC_IRQn    = 116,              /*!< 116  Week timer 0 one second alarm interrupt                              */
  MEC_WKTMR0_SUBSEC_IRQn    = 117,              /*!< 117  Week timer 0 sub-second alarm interrupt                              */
  MEC_WKTMR0_PWR_IRQn       = 118,              /*!< 118  Week timer 0 sys power present interrupt                             */
  MEC_RTC0_CLK_IRQn         = 119,              /*!< 119  RTC 0 clock interrupt                                                */
  MEC_RTC0_ALARM_IRQn       = 120,              /*!< 120  RTC 0 alarm interrupt                                                */
  MEC_VCI_OVRD_IN_IRQn      = 121,              /*!< 121  VCI0 override in interrupt                                           */
  MEC_VCI_IN0_IRQn          = 122,              /*!< 122  VCI0 IN0 interrupt                                                   */
  MEC_VCI_IN1_IRQn          = 123,              /*!< 123  VCI0 IN1 interrupt                                                   */
  MEC_VCI_IN2_IRQn          = 124,              /*!< 124  VCI0 IN2 interrupt                                                   */
  MEC_VCI_IN3_IRQn          = 125,              /*!< 125  VCI0 IN3 interrupt                                                   */
  MEC_PS2CTL0_WK0A_IRQn     = 129,              /*!< 129  PS2 Controller 0 Wake 0A start bit detected interrupt                */
  MEC_PS2CTL0_WK0B_IRQn     = 130,              /*!< 130  PS2 Controller Wake 0B start bit detected interrupt                  */
  MEC_PS2CTL1_WK1B_IRQn     = 132,              /*!< 132  PS2 Controller 1 Wake 0B start bit detected interrupt                */
  MEC_KSCAN0_INT_IRQn       = 135,              /*!< 135  KSCAN interrupt                                                      */
  MEC_BTMR0_IRQn            = 136,              /*!< 136  Basic Timer 0 interrupt                                              */
  MEC_BTMR1_IRQn            = 137,              /*!< 137  Basic Timer 1 interrupt                                              */
  MEC_BTMR2_IRQn            = 138,              /*!< 138  Basic Timer 2 interrupt                                              */
  MEC_BTMR3_IRQn            = 139,              /*!< 139  Basic Timer 3 interrupt                                              */
  MEC_BTMR4_IRQn            = 140,              /*!< 140  Basic Timer 4 interrupt                                              */
  MEC_BTMR5_IRQn            = 141,              /*!< 141  Basic Timer 5 interrupt                                              */
  MEC_CTMR0_IRQn            = 142,              /*!< 142  Counter-Timer 0 interrupt                                            */
  MEC_CTMR1_IRQn            = 143,              /*!< 143  16-bit Event Counter/Timer 1 interrupt                               */
  MEC_CTMR2_IRQn            = 144,              /*!< 144  16-bit Event Counter/Timer 2 interrupt                               */
  MEC_CTMR3_IRQn            = 145,              /*!< 145  16-bit Event Counter/Timer 3 interrupt                               */
  MEC_CCT0_TMR_IRQn         = 146,              /*!< 146  Capture and compare timer interrupt                                  */
  MEC_CCT0_CAP0_IRQn        = 147,              /*!< 147  Capture and compare timer capture 0 interrupt                        */
  MEC_CCT0_CAP1_IRQn        = 148,              /*!< 148  Capture and compare timer capture 1 interrupt                        */
  MEC_CCT0_CAP2_IRQn        = 149,              /*!< 149  Capture and compare timer capture 2 interrupt                        */
  MEC_CCT0_CAP3_IRQn        = 150,              /*!< 150  Capture and compare timer capture 3 interrupt                        */
  MEC_CCT0_CAP4_IRQn        = 151,              /*!< 151  Capture and compare timer capture 4 interrupt                        */
  MEC_CCT0_CAP5_IRQn        = 152,              /*!< 152  Capture and compare timer capture 5 interrupt                        */
  MEC_CCT0_CMP0_IRQn        = 153,              /*!< 153  Capture and compare timer compare 0 interrupt                        */
  MEC_CCT0_CMP1_IRQn        = 154,              /*!< 154  Capture and compare timer compare 1 interrupt                        */
  MEC_EEPROM_CTRL0_IRQn     = 155,              /*!< 155  EEPROM Controller 0 interrupt                                        */
  MEC_ESPI_VWEN_IRQn        = 156,              /*!< 156  eSPI IO Virtual Wire channel enable change interrupt                 */
  MEC_I2C_SMB4_IRQn         = 158,              /*!< 158  I2C_SMB4 interrupt                                                   */
  MEC_TACH3_IRQn            = 159,              /*!< 159  TACH 3 interrupt                                                     */
  MEC_ESPI_TAF_DONE_IRQn    = 166,              /*!< 166  eSPI TAF Done interrupt                                              */
  MEC_ESPI_TAF_ERR_IRQn     = 167,              /*!< 167  eSPI TAF Error interrupt                                             */
  MEC_WDT0_IRQn             = 171,              /*!< 171  Watch Dog timer 0 interrupt                                          */
  MEC_GLUE_IRQn             = 172,              /*!< 172  Glue logic interrupt                                                 */
  MEC_PCR_CLKMON_IRQn       = 174,              /*!< 174  PCR 32KHz clock monitor                                              */
  MEC_ACPI_EC0_IRQn         = 175,              /*!< 175  ACPI EC 0 combined interrupt. No GIRQ                                */
  MEC_ACPI_EC1_IRQn         = 176,              /*!< 176  ACPI EC 1 combined interrupt. No GIRQ                                */
  MEC_ACPI_EC2_IRQn         = 177,              /*!< 177  ACPI EC 2 combined interrupt. No GIRQ                                */
  MEC_ACPI_EC3_IRQn         = 178,              /*!< 178  ACPI EC 3 combined interrupt. No GIRQ                                */
  MEC_ACPI_EC4_IRQn         = 179,              /*!< 179  ACPI EC 4 combined interrupt. No GIRQ                                */
  MEC_ACPI_PM1_IRQn         = 180,              /*!< 180  ACPI PM1 combined interrupt. No GIRQ                                 */
  MEC_UART2_IRQn            = 183,              /*!< 183  UART 2 interrupt                                                     */
  MEC_BRT0_IRQn             = 193               /*!< 193  Boot-ROM Watch Dog timer 0 interrupt                                 */
} IRQn_Type;



/* =========================================================================================================================== */
/* ================                           Processor and Core Peripheral Section                           ================ */
/* =========================================================================================================================== */

/* ===========================  Configuration of the ARM Cortex-M4 Processor and Core Peripherals  =========================== */
#define __CM4_REV                 0x0201U       /*!< CM4 Core Revision                                                         */
#define __NVIC_PRIO_BITS               3        /*!< Number of Bits used for Priority Levels                                   */
#define __Vendor_SysTickConfig         0        /*!< Set to 1 if different SysTick Config is used                              */
#define __MPU_PRESENT                  1        /*!< MPU present                                                               */
#define __FPU_PRESENT                  1        /*!< FPU present                                                               */


/** @} */ /* End of group Configuration_of_CMSIS */

#include "core_cm4.h"                           /*!< ARM Cortex-M4 processor and core peripherals                              */

#ifndef __IM                                    /*!< Fallback for older CMSIS versions                                         */
  #define __IM   __I
#endif
#ifndef __OM                                    /*!< Fallback for older CMSIS versions                                         */
  #define __OM   __O
#endif
#ifndef __IOM                                   /*!< Fallback for older CMSIS versions                                         */
  #define __IOM  __IO
#endif


/* ========================================  Start of section using anonymous unions  ======================================== */
#if defined (__CC_ARM)
  #pragma push
  #pragma anon_unions
#elif defined (__ICCARM__)
  #pragma language=extended
#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
  #pragma clang diagnostic push
  #pragma clang diagnostic ignored "-Wc11-extensions"
  #pragma clang diagnostic ignored "-Wreserved-id-macro"
  #pragma clang diagnostic ignored "-Wgnu-anonymous-struct"
  #pragma clang diagnostic ignored "-Wnested-anon-types"
#elif defined (__GNUC__)
  /* anonymous unions are enabled by default */
#elif defined (__TMS470__)
  /* anonymous unions are enabled by default */
#elif defined (__TASKING__)
  #pragma warning 586
#elif defined (__CSMC__)
  /* anonymous unions are enabled by default */
#else
  #warning Not supported compiler type
#endif

#include <common/mec5_acpi_ec_v1.h>
#include <common/mec5_acpi_pm1_v1.h>
#include <common/mec5_adc_v2.h>
#include <common/mec5_bbled_v1.h>
#include <common/mec5_bcl_v1.h>
#include <common/mec5_bdp_v1.h>
#include <common/mec5_btmr_v1.h>
#include <common/mec5_cct_v1_1.h>
#include <common/mec5_chip_cfg_v1_2.h>
#include <common/mec5_cpu_stall_v1.h>
#include <common/mec5_ctmr_v1.h>
#include <common/mec5_dmac_ch16_v2.h>
#include <common/mec5_ecia_v1_5.h>
#include <common/mec5_ecs_v2_5.h>
#include <common/mec5_eeprom_ctrl_v1.h>
#include <common/mec5_emi_v2.h>
#include <common/mec5_espi_io_v1_5.h>
#include <common/mec5_espi_mem_v1_5.h>
#include <common/mec5_espi_taf_v1_5.h>
#include <common/mec5_espi_vw_v1_5.h>
#include <common/mec5_gluelog_v1.h>
#include <common/mec5_gpio_8f_6port_v1_5.h>
#include <common/mec5_gspi_v2.h>
#include <common/mec5_htmr_v1.h>
#include <common/mec5_i2c_smb_v3_8.h>
#include <common/mec5_kbc_v1.h>
#include <common/mec5_kscan_v1.h>
#include <common/mec5_mbox_v1.h>
#include <common/mec5_pcr_v2_1.h>
#include <common/mec5_peci_v1.h>
#include <common/mec5_port92_v1.h>
#include <common/mec5_prochot_v1.h>
#include <common/mec5_ps2_v1.h>
#include <common/mec5_pwm_v1.h>
#include <common/mec5_qspi_v2_1.h>
#include <common/mec5_rcid_v1.h>
#include <common/mec5_rpmfan_v1.h>
#include <common/mec5_rtc_v1.h>
#include <common/mec5_rtmr_v1.h>
#include <common/mec5_tach_v1.h>
#include <common/mec5_tfdp_v1.h>
#include <common/mec5_uart_v1_5.h>
#include <common/mec5_vbat_mem_128b_v1.h>
#include <common/mec5_vbatr_v1_5.h>
#include <common/mec5_vci_v1_5.h>
#include <common/mec5_wdt_v2.h>
#include <common/mec5_wktmr_bgpo_v1.h>

/* =========================================================================================================================== */
/* ================                          Device Specific Peripheral Address Map                           ================ */
/* =========================================================================================================================== */


/** @addtogroup Device_Peripheral_peripheralAddr
  * @{
  */

#define MEC_CPU_STALL_BASE          0x08000000UL
#define MEC_WDT0_BASE               0x40000400UL
#define MEC_BRT0_BASE               0x40000420UL
#define MEC_BTMR0_BASE              0x40000C00UL
#define MEC_BTMR1_BASE              0x40000C20UL
#define MEC_BTMR2_BASE              0x40000C40UL
#define MEC_BTMR3_BASE              0x40000C60UL
#define MEC_BTMR4_BASE              0x40000C80UL
#define MEC_BTMR5_BASE              0x40000CA0UL
#define MEC_CTMR0_BASE              0x40000D00UL
#define MEC_CTMR1_BASE              0x40000D20UL
#define MEC_CTMR2_BASE              0x40000D40UL
#define MEC_CTMR3_BASE              0x40000D60UL
#define MEC_CCT0_BASE               0x40001000UL
#define MEC_RCID0_BASE              0x40001400UL
#define MEC_RCID1_BASE              0x40001480UL
#define MEC_RCID2_BASE              0x40001500UL
#define MEC_DMAC_BASE               0x40002400UL
#define MEC_EEPROM_CTRL0_BASE       0x40002C00UL
#define MEC_PROCHOT_BASE            0x40003400UL
#define MEC_I2C_SMB0_BASE           0x40004000UL
#define MEC_I2C_SMB1_BASE           0x40004400UL
#define MEC_I2C_SMB2_BASE           0x40004800UL
#define MEC_I2C_SMB3_BASE           0x40004C00UL
#define MEC_I2C_SMB4_BASE           0x40005000UL
#define MEC_PWM0_BASE               0x40005800UL
#define MEC_PWM1_BASE               0x40005810UL
#define MEC_PWM2_BASE               0x40005820UL
#define MEC_PWM3_BASE               0x40005830UL
#define MEC_PWM4_BASE               0x40005840UL
#define MEC_PWM5_BASE               0x40005850UL
#define MEC_PWM6_BASE               0x40005860UL
#define MEC_PWM7_BASE               0x40005870UL
#define MEC_PWM8_BASE               0x40005880UL
#define MEC_TACH0_BASE              0x40006000UL
#define MEC_TACH1_BASE              0x40006010UL
#define MEC_TACH2_BASE              0x40006020UL
#define MEC_TACH3_BASE              0x40006030UL
#define MEC_PECI0_BASE              0x40006400UL
#define MEC_RTMR0_BASE              0x40007400UL
#define MEC_ADC0_BASE               0x40007C00UL
#define MEC_ESPI_TAF_COMM_BASE      0x40071000UL
#define MEC_ESPI_TAF_BASE           0x40008000UL
#define MEC_TFDP0_BASE              0x40008C00UL
#define MEC_PS2CTL0_BASE            0x40009000UL
#define MEC_PS2CTL1_BASE            0x40009040UL
#define MEC_GSPI0_BASE              0x40009400UL
#define MEC_GSPI1_BASE              0x40009480UL
#define MEC_HTMR0_BASE              0x40009800UL
#define MEC_HTMR1_BASE              0x40009820UL
#define MEC_KSCAN0_BASE             0x40009C00UL
#define MEC_RPMFAN0_BASE            0x4000A000UL
#define MEC_RPMFAN1_BASE            0x4000A080UL
#define MEC_VBATR_BASE              0x4000A400UL
#define MEC_VBATM_BASE              0x4000A800UL
#define MEC_WKTMR0_BASE             0x4000AC80UL
#define MEC_VCI_BASE                0x4000AE00UL
#define MEC_BBLED0_BASE             0x4000B800UL
#define MEC_BBLED1_BASE             0x4000B900UL
#define MEC_BBLED2_BASE             0x4000BA00UL
#define MEC_BBLED3_BASE             0x4000BB00UL
#define MEC_BCL0_BASE               0x4000CD00UL
#define MEC_ECIA0_BASE              0x4000E000UL
#define MEC_ECS_BASE                0x4000FC00UL
#define MEC_QSPI0_BASE              0x40070000UL
#define MEC_PCR_BASE                0x40080100UL
#define MEC_GPIO_BASE               0x40081000UL
#define MEC_MBOX0_BASE              0x400F0000UL
#define MEC_KBC0_BASE               0x400F0400UL
#define MEC_ACPI_EC0_BASE           0x400F0800UL
#define MEC_ACPI_EC1_BASE           0x400F0C00UL
#define MEC_ACPI_EC2_BASE           0x400F1000UL
#define MEC_ACPI_EC3_BASE           0x400F1400UL
#define MEC_ACPI_EC4_BASE           0x400F1800UL
#define MEC_ACPI_PM1_BASE           0x400F1C00UL
#define MEC_PORT92_BASE             0x400F2000UL
#define MEC_UART0_BASE              0x400F2400UL
#define MEC_UART1_BASE              0x400F2800UL
#define MEC_UART2_BASE              0x400F2C00UL
#define MEC_GLUE_BASE               0x400F3C00UL
#define MEC_EMI0_BASE               0x400F4000UL
#define MEC_EMI1_BASE               0x400F4400UL
#define MEC_EMI2_BASE               0x400F4800UL
#define MEC_RTC0_BASE               0x400F5000UL
#define MEC_BDP0_BASE               0x400F8000UL
#define MEC_CHIP_CFG_BASE           0x400FFF00UL
#define MEC_ESPI_IO_BASE            0x400F3400UL
#define MEC_ESPI_MEM_BASE           0x400F3800UL
#define MEC_ESPI_VW_BASE            0x400F9C00UL

/** @} */ /* End of group Device_Peripheral_peripheralAddr */


/* =========================================================================================================================== */
/* ================                                  Peripheral declaration                                   ================ */
/* =========================================================================================================================== */


/** @addtogroup Device_Peripheral_declaration
  * @{
  */

#define MEC_CPU_STALL               ((MEC_CPU_STALL_Type*)     MEC_CPU_STALL_BASE)
#define MEC_WDT0                    ((MEC_WDT_Type*)           MEC_WDT0_BASE)
#define MEC_BRT0                    ((MEC_BRT_Type*)           MEC_BRT0_BASE)
#define MEC_BTMR0                   ((MEC_BTMR_Type*)          MEC_BTMR0_BASE)
#define MEC_BTMR1                   ((MEC_BTMR_Type*)          MEC_BTMR1_BASE)
#define MEC_BTMR2                   ((MEC_BTMR_Type*)          MEC_BTMR2_BASE)
#define MEC_BTMR3                   ((MEC_BTMR_Type*)          MEC_BTMR3_BASE)
#define MEC_BTMR4                   ((MEC_BTMR_Type*)          MEC_BTMR4_BASE)
#define MEC_BTMR5                   ((MEC_BTMR_Type*)          MEC_BTMR5_BASE)
#define MEC_CTMR0                   ((MEC_CTMR_Type*)          MEC_CTMR0_BASE)
#define MEC_CTMR1                   ((MEC_CTMR_Type*)          MEC_CTMR1_BASE)
#define MEC_CTMR2                   ((MEC_CTMR_Type*)          MEC_CTMR2_BASE)
#define MEC_CTMR3                   ((MEC_CTMR_Type*)          MEC_CTMR3_BASE)
#define MEC_CCT0                    ((MEC_CCT_Type*)           MEC_CCT0_BASE)
#define MEC_RCID0                   ((MEC_RCID_Type*)          MEC_RCID0_BASE)
#define MEC_RCID1                   ((MEC_RCID_Type*)          MEC_RCID1_BASE)
#define MEC_RCID2                   ((MEC_RCID_Type*)          MEC_RCID2_BASE)
#define MEC_DMAC                    ((MEC_DMAC_Type*)          MEC_DMAC_BASE)
#define MEC_EEPROM_CTRL0            ((MEC_EEPROM_CTRL_Type*)   MEC_EEPROM_CTRL0_BASE)
#define MEC_PROCHOT                 ((MEC_PHOT_Type*)          MEC_PROCHOT_BASE)
#define MEC_I2C_SMB0                ((MEC_I2C_SMB_Type*)       MEC_I2C_SMB0_BASE)
#define MEC_I2C_SMB1                ((MEC_I2C_SMB_Type*)       MEC_I2C_SMB1_BASE)
#define MEC_I2C_SMB2                ((MEC_I2C_SMB_Type*)       MEC_I2C_SMB2_BASE)
#define MEC_I2C_SMB3                ((MEC_I2C_SMB_Type*)       MEC_I2C_SMB3_BASE)
#define MEC_I2C_SMB4                ((MEC_I2C_SMB_Type*)       MEC_I2C_SMB4_BASE)
#define MEC_PWM0                    ((MEC_PWM_Type*)           MEC_PWM0_BASE)
#define MEC_PWM1                    ((MEC_PWM_Type*)           MEC_PWM1_BASE)
#define MEC_PWM2                    ((MEC_PWM_Type*)           MEC_PWM2_BASE)
#define MEC_PWM3                    ((MEC_PWM_Type*)           MEC_PWM3_BASE)
#define MEC_PWM4                    ((MEC_PWM_Type*)           MEC_PWM4_BASE)
#define MEC_PWM5                    ((MEC_PWM_Type*)           MEC_PWM5_BASE)
#define MEC_PWM6                    ((MEC_PWM_Type*)           MEC_PWM6_BASE)
#define MEC_PWM7                    ((MEC_PWM_Type*)           MEC_PWM7_BASE)
#define MEC_PWM8                    ((MEC_PWM_Type*)           MEC_PWM8_BASE)
#define MEC_TACH0                   ((MEC_TACH_Type*)          MEC_TACH0_BASE)
#define MEC_TACH1                   ((MEC_TACH_Type*)          MEC_TACH1_BASE)
#define MEC_TACH2                   ((MEC_TACH_Type*)          MEC_TACH2_BASE)
#define MEC_TACH3                   ((MEC_TACH_Type*)          MEC_TACH3_BASE)
#define MEC_PECI0                   ((MEC_PECI_Type*)          MEC_PECI0_BASE)
#define MEC_RTMR0                   ((MEC_RTMR_Type*)          MEC_RTMR0_BASE)
#define MEC_ADC0                    ((MEC_ADC_Type*)           MEC_ADC0_BASE)
#define MEC_ESPI_TAF_COMM           ((MEC_ESPI_TAF_COMM_Type*) MEC_ESPI_TAF_COMM_BASE)
#define MEC_ESPI_TAF                ((MEC_ESPI_TAF_Type*)      MEC_ESPI_TAF_BASE)
#define MEC_TFDP0                   ((MEC_TFDP_Type*)          MEC_TFDP0_BASE)
#define MEC_PS2CTL0                 ((MEC_PS2_Type*)           MEC_PS2CTL0_BASE)
#define MEC_PS2CTL1                 ((MEC_PS2_Type*)           MEC_PS2CTL1_BASE)
#define MEC_GSPI0                   ((MEC_GSPI_Type*)          MEC_GSPI0_BASE)
#define MEC_GSPI1                   ((MEC_GSPI_Type*)          MEC_GSPI1_BASE)
#define MEC_HTMR0                   ((MEC_HTMR_Type*)          MEC_HTMR0_BASE)
#define MEC_HTMR1                   ((MEC_HTMR_Type*)          MEC_HTMR1_BASE)
#define MEC_KSCAN0                  ((MEC_KSCAN_Type*)         MEC_KSCAN0_BASE)
#define MEC_RPMFAN0                 ((MEC_RPMFAN_Type*)        MEC_RPMFAN0_BASE)
#define MEC_RPMFAN1                 ((MEC_RPMFAN_Type*)        MEC_RPMFAN1_BASE)
#define MEC_VBATR                   ((MEC_VBATR_Type*)         MEC_VBATR_BASE)
#define MEC_VBATM                   ((MEC_VBATM_Type*)         MEC_VBATM_BASE)
#define MEC_WKTMR0                  ((MEC_WKTMR_Type*)         MEC_WKTMR0_BASE)
#define MEC_VCI                     ((MEC_VCI_Type*)           MEC_VCI_BASE)
#define MEC_BBLED0                  ((MEC_BBLED_Type*)         MEC_BBLED0_BASE)
#define MEC_BBLED1                  ((MEC_BBLED_Type*)         MEC_BBLED1_BASE)
#define MEC_BBLED2                  ((MEC_BBLED_Type*)         MEC_BBLED2_BASE)
#define MEC_BBLED3                  ((MEC_BBLED_Type*)         MEC_BBLED3_BASE)
#define MEC_BCL0                    ((MEC_BCL_Type*)           MEC_BCL0_BASE)
#define MEC_ECIA0                   ((MEC_ECIA_Type*)          MEC_ECIA0_BASE)
#define MEC_ECS                     ((MEC_ECS_Type*)           MEC_ECS_BASE)
#define MEC_QSPI0                   ((MEC_QSPI_Type*)          MEC_QSPI0_BASE)
#define MEC_PCR                     ((MEC_PCR_Type*)           MEC_PCR_BASE)
#define MEC_GPIO                    ((MEC_GPIO_Type*)          MEC_GPIO_BASE)
#define MEC_MBOX0                   ((MEC_MBOX_Type*)          MEC_MBOX0_BASE)
#define MEC_KBC0                    ((MEC_KBC_Type*)           MEC_KBC0_BASE)
#define MEC_ACPI_EC0                ((MEC_ACPI_EC_Type*)       MEC_ACPI_EC0_BASE)
#define MEC_ACPI_EC1                ((MEC_ACPI_EC_Type*)       MEC_ACPI_EC1_BASE)
#define MEC_ACPI_EC2                ((MEC_ACPI_EC_Type*)       MEC_ACPI_EC2_BASE)
#define MEC_ACPI_EC3                ((MEC_ACPI_EC_Type*)       MEC_ACPI_EC3_BASE)
#define MEC_ACPI_EC4                ((MEC_ACPI_EC_Type*)       MEC_ACPI_EC4_BASE)
#define MEC_ACPI_PM1                ((MEC_ACPI_PM1_Type*)      MEC_ACPI_PM1_BASE)
#define MEC_PORT92                  ((MEC_PORT92_Type*)        MEC_PORT92_BASE)
#define MEC_UART0                   ((MEC_UART_Type*)          MEC_UART0_BASE)
#define MEC_UART1                   ((MEC_UART_Type*)          MEC_UART1_BASE)
#define MEC_UART2                   ((MEC_UART_Type*)          MEC_UART2_BASE)
#define MEC_GLUE                    ((MEC_GLUE_Type*)          MEC_GLUE_BASE)
#define MEC_EMI0                    ((MEC_EMI_Type*)           MEC_EMI0_BASE)
#define MEC_EMI1                    ((MEC_EMI_Type*)           MEC_EMI1_BASE)
#define MEC_EMI2                    ((MEC_EMI_Type*)           MEC_EMI2_BASE)
#define MEC_RTC0                    ((MEC_RTC_Type*)           MEC_RTC0_BASE)
#define MEC_BDP0                    ((MEC_BDP_Type*)           MEC_BDP0_BASE)
#define MEC_CHIP_CFG                ((MEC_CHIP_CFG_Type*)      MEC_CHIP_CFG_BASE)
#define MEC_ESPI_IO                 ((MEC_ESPI_IO_Type*)       MEC_ESPI_IO_BASE)
#define MEC_ESPI_MEM                ((MEC_ESPI_MEM_Type*)      MEC_ESPI_MEM_BASE)
#define MEC_ESPI_VW                 ((MEC_ESPI_VW_Type*)       MEC_ESPI_VW_BASE)

/** @} */ /* End of group Device_Peripheral_declaration */


/* =========================================  End of section using anonymous unions  ========================================= */
#if defined (__CC_ARM)
  #pragma pop
#elif defined (__ICCARM__)
  /* leave anonymous unions enabled */
#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
  #pragma clang diagnostic pop
#elif defined (__GNUC__)
  /* anonymous unions are enabled by default */
#elif defined (__TMS470__)
  /* anonymous unions are enabled by default */
#elif defined (__TASKING__)
  #pragma warning restore
#elif defined (__CSMC__)
  /* anonymous unions are enabled by default */
#endif

#ifdef __cplusplus
}
#endif

#endif /* MEC1743_QSZ_H */


/** @} */ /* End of group MEC1743_QSZ */

/** @} */ /* End of group Microchip Technolgy Inc. */
